1. Field of the Invention
This invention relates to a computer and, more particularly, to a bus interface unit having a plurality of input buffers which can be selectively deactivated depending on the current power state of the computer and/or activity upon a central processing unit ("CPU") local bus.
2. Description of the Related Art
Power consumption in an electronic device is always a significant concern. Longevity of the power supply, heat dissipation, physical size, weight, efficiency and other related characteristics are paramount in designing the electronic device. These characteristics become exceptionally critical when the device is a self-sufficient portable unit.
A portable unit is one in which power is supplied from a battery during times when the unit is decoupled from its main power source, e.g., a 110 volt ac supply. In some instances, the battery functions as an auxiliary power source to ensure critical circuits are kept alive and to retain information stored in memory. In other instances, the battery functions as the main power source to fully power the device in its operational state.
Various types of portable units can be powered from a battery including, for example, a computer. Modern portable computers are called upon to perform at increasingly higher levels. For example, a high performance portable computer may employ a high speed CPU and multiple buses between the CPU and numerous input/output devices. Multiple buses may include a CPU local bus connected directly to the CPU, a peripheral bus connected to slower input/output devices, and a mezzanine bus connected between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture ("ISA") bus, an enhanced ISA ("EISA") bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interface ("PCI") bus to which higher speed input/output devices can be connected.
Coupled between the various busses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the "south bridge".
The north bridge bus interface unit must accommodate the high speed clocking cycles of the CPU. In many instances, the internal clock of a modern day CPU will transition at rates exceeding several hundred MHz. In order to accommodate this speed, signal swing within the CPU bus must be somewhat limited. For example, complimentary metal oxide semiconductor ("CMOS") signal swings are too large even though CMOS technology consumes minimal power.
Recently, another standard for electrical signal transmission called Gunning Transceiver Logic ("GTL") has been devised which can accommodate the higher speeds of modern CPU buses. Typically, a GTL signal will extend minimally above and below a reference voltage. In order to illustrate GTL usage in a modern Pentium.RTM. Pro CPU bus operating in excess of 50 MHz, GTL signal swings are typically constrained less than 200 millivolts from a reference voltage.
Smaller voltage swings may allow higher clock speeds. However, a GTL bus is an "open-collector" bus which generally requires pull-up resistors near terminating ends of each bus conductor. Significant power consumption is due, in part, to the operation of the pull-up resistors. In addition, GTL or GTL+ advocated by Intel Corporation requires a level-sensitive differential amplifier coupled to receive the GTL signals. Regardless of whether the signal is active or inactive, the differential amplifier nonetheless remains on and consumes power. Embodied upon the north bridge and associated with each conductor of the CPU bus is a constantly on differential amplifier.
It would be desirable to produce a portable computer which can accommodate a high speed CPU bus using, for example, differential signals set forth possibly in a GTL, GTL+, 1394 or serial link format. However, to produce a viable portable computer having the aforesaid performance characteristics, a mechanism must be derived which can monitor the CPU bus and periodically reduce power consumption in the critical elements of the portable computer. Namely, an improvement is needed for dynamically reducing power consumption of the differential amplifiers within the north bridge when the differential signals sent across the CPU bus are inactive. Reducing power consumption in a portable computer having a bus which employs differential signals would help extend the battery life of the computer.